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1 ? HI5731 12-bit, 100msps, high speed d/a converter the HI5731 is a 12-bit, 100msps, d/a converter which is implemented in the intersil b icmos 10v (hbc-10) process. operating from +5v and -5.2v, the converter provides -20.48ma of full scale output current and includes an input data register and bandgap voltage reference. low glitch energy and excellent frequency domain performance are achieved using a segmented architecture. the digital inputs are ttl/cmos compatible and translated internally to ecl. all internal logic is implemented in ecl to achieve high switching speed with low noise. the addition of laser trimming assures 12-bit linearity is maintained along the entire transfer curve. pinout HI5731 (pdip, soic) top view features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . . 100msps ? low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mw ? integral linearity error . . . . . . . . . . . . . . . . . . . . 0.75 lsb ? low glitch energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pv-s ? ttl/cmos compatible inputs ? improved hold time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns ? excellent spurious free dynamic range applications ? cellular base stations ? gsm base stations ? wireless communications ? direct digital frequency synthesis ? signal reconstruction ? test equipment ? high resolution imaging systems ? arbitrary waveform generators ordering information part number temp. range ( o c) package pkg. no. HI5731bip -40 to 85 28 ld pdip e28.6 HI5731bib -40 to 85 28 ld soic m28.3 HI5731-evs 25 evaluation board (soic) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dgnd ref out ctrl out ctrl in r set i out artn dv ee dgnd dv cc clock agnd av ee i out data sheet april 2001 fn4070.8 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 typical application circuit functional block diagram d9 (3) d8 (4) d7 (5) d6 (6) d5 (7) d4 (8) d3 (9) d2 (10) d9 d8 d7 d6 d5 d4 d3 d2 +5v dv cc (16) 0.01 f dgnd (17, 28) clk (15) -5.2v (av ee ) 0.1 f (19) artn (22) av ee d/a out (21) i out (20) i out (23) r set 976 ? 64 ? (24) ctrl in HI5731 d10 d11 d11 (msb) (1) d10 (2) dv ee (18) - 5.2v (av ee ) 0.01 f (25) ctrl out (26) ref out 64 ? 0.1 f - 5.2v (dv ee ) 0.01 f 0.1 f (27) agnd 50 ? d1 (11) d0 (lsb) (12) d1 d0 upper slave i out (lsb) d0 d1 d2 d3 d4 d5 d6 d9 d7 d8 4-bit decoder i out + - ctrl ref out r set ctrl 25 ? 12-bit master register av ee agnd dv ee dgnd dv cc 15 switched current cells d10 (msb) d11 register data buffer/ level shifter overdriveable voltage reference clk ref cell in out 8 lsbs current cells r2r network 227 ? 227 ? 15 15 artn HI5731
3 absolute maximum rati ngs thermal information digital supply voltage v cc to dgnd . . . . . . . . . . . . . . . . . . . +5.5v negative digital supply voltage dv ee to dgnd . . . . . . . . . . -5.5v negative analog supply voltage av ee to agnd, artn. . . . . -5.5v digital input voltages (d11-d0, clk) to dgnd . . . . . dv cc to -0.5v internal reference output current. . . . . . . . . . . . . . . . . . . . 2.5ma voltage from ctrl in to av ee . . . . . . . . . . . . . . . . . . . . 2.5v to 0v control amplifier output current . . . . . . . . . . . . . . . . . . . . . 2.5ma reference input voltage range. . . . . . . . . . . . . . . . . .-3.7v to av ee analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 30ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 maximum junction temperature HI5731bix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. electrical specifications av ee , dv ee = -4.94 to -5.46v, v cc = +4.75 to +5.25v, v ref = internal t a = 25 o c for all typical values parameter test conditions HI5731bi t a = -40 o c to 85 o c units min typ max system performance resolution 12 - - bits integral linearity error, inl (note 4) (?best fit? straight line) - 0.75 1.5 lsb differential linearity error, dnl (note 4) - 0.5 1.0 lsb offset error, i os (note 4) - 20 75 a full scale gain error, fse (notes 2, 4) - 1 10 % full scale gain drift with internal reference - 1 50 - ppm fsr/ o c offset drift coefficient (note 3) - - 0.05 a/ o c full scale output current, i fs -20.48- ma output voltage compliance range (note 3) -1.25 - 0 v dynamic characteristics throughput rate (note 3) 100 - - msps output voltage full scale step settling time, t sett , full scale to 0.5 lsb error band r l = 50 ? (note 3) -20- ns singlet glitch area, ge (peak) r l = 50 ? (note 3) - 5 - pv-s doublet glitch area, (net) -3-pv-s output slew rate r l = 50 ? , dac operating in latched mode (note 3) - 1,000 - v/ s output rise time r l = 50 ? , dac operating in latched mode (note 3) - 675 - ps output fall time r l = 50 ? , dac operating in latched mode (note 3) - 470 - ps spurious free dynamic range within a window (note 3) f clk = 10msps, f out = 1.23mhz, 2mhz span - 85 - dbc f clk = 20msps, f out = 5.055mhz, 2mhz span - 77 - dbc f clk = 40msps, f out = 16mhz, 10mhz span - 75 - dbc f clk = 50msps, f out = 10.1mhz, 2mhz span - 80 - dbc f clk = 80msps, f out = 5.1mhz, 2mhz span - 78 - dbc f clk = 100msps, f out = 10.1mhz, 2mhz span - 79 - dbc HI5731
4 spurious free dynamic range to nyquist (note 3) f clk = 40msps, f out = 2.02mhz, 20mhz span - 70 - dbc f clk = 80msps, f out = 2.02mhz, 40mhz span - 70 - dbc f clk = 100msps, f out = 2.02mhz, 50mhz span - 69 - dbc reference/control amplifier internal reference voltage, v ref (note 4) -1.27 -1.23 -1.17 v internal reference voltage drift (note 3) - 175 - v/ o c internal reference output current sink/source capability (note 3) -125 - +50 a internal reference load regulation i ref = 0 to i ref = -125 a-50- v input impedance at ref out pin (note 3) - 1.4 - k ? amplifier large signal bandwidth (0.6v p-p ) sine wave input, to slew rate limited (note 3) - 3 - mhz amplifier small signal bandwidth (0.1v p-p ) sine wave input, to -3db loss (note 3) - 10 - mhz reference input impedance (note 3) - 12 - k ? reference input multiplying bandwidth (ctl in) r l = 50 ? , 100mv sine wave, to -3db loss at i out (note 3) - 200 - mhz digital inputs (d9-d0, clk, invert) input logic high voltage, v ih (note 4) 2.0 - - v input logic low voltage, v il (note 4) - - 0.8 v input logic current, i ih (note 4) - - 400 a input logic current, i il (note 4) - - 700 a digital input capacitance, c in (note 3) - 3.0 - pf timing characteristics data setup time, t su see figure 1 (note 3) 3.0 2.0 - ns data hold time, t hld see figure 1 (note 3) 0.5 0.25 - ns propagation delay time, t pd see figure 1 (note 3) - 4.5 - ns clk pulse width, t pw1 , t pw2 see figure 1 (note 3) 3.0 - - ns power supply characteristics i eea (note 4) - 42 50 ma i eed (note 4) - 70 85 ma i ccd (note 4) - 13 20 ma power dissipation (note 4) - 650 - mw power supply rejection ratio v cc 5%, v ee 5% - 5 - a/v notes: 2. gain error measured as the error in the ratio between the full scale output current and the current through r set (typically 1.28ma). ideally the ratio should be 16. 3. parameter guaranteed by design or c haracterization and not production tested. 4. all devices are 100% tested at 25 o c. 5. dynamic range must be limited to a 1v swing within the compliance range. electrical specifications av ee , dv ee = -4.94 to -5.46v, v cc = +4.75 to +5.25v, v ref = internal t a = 25 o c for all typical values (continued) parameter test conditions HI5731bi t a = -40 o c to 85 o c units min typ max HI5731
5 timing diagrams figure 1. full scale settling time diagram figure 2. peak glitch area (singlet) measurement method figure 3. propagation delay, setup time, hold time and minimum pulse width diagram clk d11-d0 i out 50% t sett 1 / 2 lsb error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk d11-d0 i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld HI5731
6 typical performance curves figure 4. typical power dissipation over temperature figure 5. typical reference voltage over temperature figure 6. typical inl figure 7. typical dnl figure 8. offset current over temperature fig ure 9. spurious free dynamic range = 87.3dbc -50 -30 -10 10 30 50 70 90 560 600 640 680 temperature (mw) clock frequency does not alter power dissipation -50 -30 -10 10 30 50 70 90 -1.29 -1.27 -1.25 -1.23 -1.21 temperature (v) 0 600 1200 1800 2400 3000 3600 4200 1.5 -0.5 0.5 1.5 code (lsb) 400 1000 1600 2200 2800 3400 4000 -0.8 -0.4 0.0 0.4 0.8 code (lsb) -40 -20 -0 20 40 60 80 100 temperature ( a) 12 16 20 24 28 ? mkr -87.33db -73khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 1.237mhz s c f c = 10msps HI5731
7 figure 10. spurious free dynamic range = 76.16dbc figure 11. spurious free dynamic range = 75.17dbc figure 12. spurious free dynamic range = -81.67dbc figure 13. spurious free dynamic range = 77dbc figure 14. spurious free dynamic range = -85.60dbc figure 15. spurious free dynamic range = 85.5dbc typical performance curves (continued) ? mkr -76.16db -53khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 5.055mhz c f c = 20msps ? mkr -75.17db -70khz 10db/ atten 20db rl -10.0dbm span 10.00mhz center 16.00mhz c s f c = 40msps ? mkr -81.67db -953khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 10.100mhz c s f c = 50msps ? mkr -77.00db -93khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 5.097mhz c f c = 80msps ? mkr -85.60db -33khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 2.027mhz s c f c = 100msps ? mkr -85.50db 73khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 5.000mhz s c f c = 100msps HI5731
8 figure 16. spurious free dynamic range = 80.5dbc figure 17. spurious free dynamic range = 72.17dbc figure 18. spurious free dynamic range = 71.16dbc fi gure 19. spurious free dynamic range = 70.5dbc figure 20. spurious free dynamic range = 70dbc typical performance curves (continued) ? mkr -80.50db -807khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 10.133mhz f c = 100msps ? mkr -72.17db -467khz 10db/ atten 20db rl -10.0dbm span 2.000mhz center 26.637mhz c s f c = 100msps ? mkr -71.16db 2.99mhz 10db/ atten 20db rl -10.0dbm c s stop frequency 20mhz start frequency 500khz f c = 40msps f o = 2.02mhz ? mkr -70.50db 1.98mhz 10db/ atten 20db rl -10.0dbm stop frequency 40mhz start frequency 500khz c s f c = 80msps f o = 2.02mhz ? mkr -70.00db 4.13mhz 10db/ atten 20db rl -10.0dbm c s stop frequency 50mhz start frequency 500khz f c = 100msps f o = 2.02mhz HI5731
9 detailed description the HI5731 is a 12-bit, current out d/a converter. the dac can convert at 100msps and runs on +5v and -5.2v supplies. the architecture is an r/2r and segmented switching current cell arrangement to reduce glitch. laser trimming is employed to tune linearity to true 12-bit leve ls. the HI5731 achieves its low power and high speed performance from an advanced bicmos process. the HI5731 consumes 650mw (typical) and has an improved hold time of only 0.25ns (typical). the HI5731 is an excellent converter fo r use in communications applications and high performance instrumentation systems. digital inputs the HI5731 is a ttl/cmos compat ible d/a. data is latched by a master register. once latched, data inputs d0 (lsb) thru d11 (msb) are internally translated from ttl to ecl. the internal latch and switching current source controls are implemented in ecl technology to maintain high switching speeds and low noise characteristics. decoder/driver the architecture employs a split r/2r ladder and segmented current source arrangement. bits d0 (lsb) thru d7 directly drive a typical r/2r network to create the binary weighted current sources. bits d8 thru d11 (msb) pass thru a ?thermometer? decoder that converts the incoming data into 15 individual segmented current source enables. this split architecture helps to improve glitch, thus resulting in a more constant glitch characte ristic across the entire output transfer function. clocks and termination the internal 12-bit register is updated on the rising edge of the clock. since the HI5731 clock rate can run to 100msps, to minimize reflections and clock noise into the part proper termination should be used. in pcb layout clock runs should be kept short and have a minimum of loads. to guarantee consistent results from board to board controlled impedance pcbs should be used with a c haracteristic line impedance z o of 50 ? . to terminate the clock line, a shunt terminator to ground is the most effective type at a 100msps clock rate. a typical value for termination can be determined by the equation: r t = z o , for the termination resistor. for a controlled impedance board with a z o of 50 ? , the r t = 50 ? . shunt termination is best used at the receiving end of the transmission line or as close to the HI5731 clk pin as possible. rise and fall times and propagation delay of the line will be affected by the shunt terminat or. the terminator should be connected to dgnd. noise reduction to reduce power supply noise, separate analog and digital power supplies should be used with 0.1 f and 0.01 f ceramic capacitors placed as close to the body of the pin descriptions pin number pin name pin description 1-12 d11 (msb) thru d0 (lsb) digital data bit 11, the most significant bit th ru digital data bit 0, the least significant bit. 15 clk data clock pin dc to 100msps. 13, 14 nc no connect. 16 dv cc digital logic supply +5v. 17, 28 dgnd digital ground. 18 dv ee -5.2v logic supply. 23 r set external resistor to set the full scale output current. i fs = 16 x (v ref out / r set ). typically 976 ? . 27 agnd analog ground supply current return pin. 19 artn analog signal return for the r/2r ladder. 21 i out current output pin. 20 i out complementary current output pin. 22 av ee -5.2v analog supply. 24 ctrl in input to the current source base rail. typically connected to ctrl out and a 0.1 f capacitor to av ee . allows external control of the current sources. 25 ctrl out control amplifier out. provides precision control of the current sources when connected to ctrl in such that i fs = 16 x (v ref out / r set ). 26 ref out -1.23v (typ) bandgap reference voltage output. can sink up to 125 a or be overdriven by an external reference capable of delivering up to 2ma. figure 21. clock line termination r t = 50 ? HI5731 dac clk z o = 50 ? HI5731
10 HI5731 as possible on the analog (av ee ) and digital (dv ee ) supplies. the analog and digital ground returns should be connected together back at the device to ensure proper operation on power up. the v cc power pin should also be decoupled with a 0.1 f capacitor. reference the internal reference of the HI5731 is a -1.23v (typical) bandgap voltage reference with 175 v/ o c of temperature drift (typical). the internal reference is connected to the control amplifier which in turn drives the segmented current cells. reference out (ref out) is internally connected to the control amplifier. the c ontrol amplifier output (ctrl out) should be used to drive the control amplifier input (ctrl in) and a 0.1 f capacitor to analog v ee . this improves settling time by providing an ac ground at the current source base node. the full scale output current is controlled by the ref out pin and the set resistor (r set ). the ratio is: i out (full scale) = (v ref out /r set ) x 16, the internal reference (ref out) can be overdriven with a more precise external reference to provide better performance over temper ature. figure 22 ill ustrates a typical external reference configuration. multiplying capability the HI5731 can operate in two different multiplying configurations. for frequencies from dc to 100khz, a signal of up to 0.6v p-p can be applied directly to the ref out pin as shown in figure 23. the signal must have a dc value such that the peak negative voltage equals -1.25v. alternately, a capacitor can be placed in series with ref out if dc multiplying is not required. the lower input bandwidth can be calculated using the following formula: for multiplying frequencies above 100khz, the ctrl in pin can be driven directly as seen in figure 24. the nominal input/output relationship is defined as: in order to prevent the full scale output current from exceeding 20.48ma, the r set resistor must be adjusted according to the following equation: the circuit in figure 24 can be tuned to adjust the lower cutoff frequency by adjusting capacitor values. table 1 below illustrates the relationship. also, the input signal must be limited to 1v p-p to avoid distortion in the dac output current caused by excessive modulation of the internal current sources. outputs the outputs i out and i out are complementary current outputs. current is steered to either i out or i out in proportion to the digital input code. the sum of the two currents is always equal to the full scale current minus one lsb. the current output can be converted to a voltage by using a load resistor. both current outputs should have the same load resistor (64 ? typically). by using a 64 ? load on the output, a 50 ? effective output resistance (r out ) is achieved due to the 227 ? ( 15%) parallel resistance seen looking back into the output. th is is the nominal value of the r2r ladder of the dac. the 50 ? output is needed for matching the output with a 50 ? line. the load resistor should figure 22. external reference configuration (26) ref out HI5731 r -5.2v -1.25v figure 23. low frequenc y multiplying bandwidth circuit ref out HI5731 c in (optional) 0.01 f rset v in ctrl out ctrl in av ee table 1. capacitor selection f in c1 c2 100khz 0.01 f1 f >1mhz 0.001 f0.1 f c in 1 2 () 1400 () f in () ------------------------------------------- . = figure 24. high frequency multiplying bandwidth circuit HI5731 ctrl in v in ctrl out av ee 200 ? c 2 c 1 50 ? ? i out ? v in 80 ? ------------- - . = r set 16v ref i out (full scale) v in peak () 80 ? ----------------------------- ?? ?? ? ----------------------------------------------------------------------------------------------- . = HI5731
11 be chosen so that the effective output resistance (r out ) matches the line resistance. the output voltage is: v out = i out x r out . i out is defined in the reference section. i out is not trimmed to 12 bits, so it is not recommended that it be used in conjunction with i out in a differential-to-single-ended application. the compliance rang e of the output is from - 1.25v to 0v, with a 1v p-p voltage swing allowed within this range. settling time the settling time of the HI5731 is measured as the time it takes for the output of the dac to settle to within a 1 / 2 lsb error band of its final value during a full scale (code 0000... to 1111.... or 1111... to 0 000...) transition. all claims made by intersil with respect to the settling time performance of the HI5731 have been fully verified by the national institute of standards and technology (nist) and are fully traceable. glitch the output glitch of the HI5731 is measured by summing the area under the switching trans ients after an update of the dac. glitch is caused by the time skew between bits of the incoming digital data. typically, the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (ttl designs). unequal delay paths through the device can also cause one current source to change before another. in order to minimize this, the intersil HI5731 employes an internal register, just prior to the current sources, which is updated on the clock edge. lastly, the worst case glitch on traditional d/a converters usually occurs at the major transitio n (i.e., code 2047 to 2048). however, due to the split arch itecture of the HI5731, the glitch is moved to the 255 to 256 transition (and every subsequent 256 code transitions t hereafter). this split r/2r segmented current source arch itecture, which decreases the amount of current switching at any one time, makes the glitch practically constant over the entire output range. by making the glitch a constant size over the entire output range this effectively integrat es this error out of the end application. in measuring the output glitch of the HI5731 the output is terminated into a 64 ? load. the glitch is measured at any one of the current cell carry (c ode 255 to 256 transition or any multiple thereof) througho ut the dacs output range. the glitch energy is calcul ated by measuring the area under the voltage-time curve. figure 26 shows the area considered as glitch when changing the dac output. units are typically specified in picovolt-seconds (pv-s). applications bipolar applications to convert the output of the HI5731 to a bipolar 4v swing, the following applications circuit is recommended. the reference can only provide 125 a of drive, so it must be buffered to create the bipola r offset current needed to generate the -2v output with all bits ?off?. the output current must be converted to a voltage and then gained up and offset to produce the proper swing. care must be taken to compensate for the voltage swing and error. table 2. input coding vs current output input code (d11-d0) i out (ma) i out (ma) 1111 1111 1111 -20.48 0 1000 0000 0000 -10.24 -10.24 0000 0000 0000 0 -20.48 (21) i out 100mhz low pass filter scope HI5731 64 ? 50 ? figure 25. glitch test circuit figure 26. measuring glitch energy a (mv) t (ns) glitch energy = ( a x t )/2 HI5731 ref out i out 1 / 2 ca2904 + - + - + - 50 ? 5k ? 1 / 2 ca2904 5k ? 60 ? 240 ? 240 ? hfa1100 v out 0.1 f figure 27. bipolar output configuration (21) (26) HI5731
12 interfacing to the hsp45106 nco-16 the hsp45106 is a 16-bit, numerically controlled oscillator (nco). the hsp45106 can be used to generate various modulation schemes for direct digital synthesis (dds) applications. figure 28 shows how to interface an HI5731 to the hsp45106. interfacing to the hsp45102 nco-12 the hsp45102 is a 12-bit, numerically controlled oscillator (nco). the hsp45102 can be used to generate various modulation schemes for direct digital synthesis (dds) applications. figure 29 shows how to interface an HI5731 to the hsp45102. this high level bl ock diagram is that of a basic psk modulator. in this example the encoder generates the psk waveform by driving the phase modulation inputs (p1, p0) of the hsp45102. the p1-0 inputs impart a phase shift to the carrier wave as defined in table 2. the data port of the hsp451 02 drives the 12-bit HI5731 dac which converts the nco output into an analog waveform. the output filter connected to the dac can be tailored to remove unwanted spurs for the desired carrier frequency. the controller is used to load the desired center frequency and control the h sp45102. the HI5731 coupled with the hsp45102 make an inexpensive psk modulator with spurious free performance down to -76dbc. definition of specifications integral linearity error, inl, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. differential linearity error, dnl, is the measure of the error in step size between adjacent codes along the converter?s transfer curve. ideally, the step size is 1 lsb from one code to the next, and the deviation from 1 lsb is known as dnl. a dnl specification of greater than -1 lsb guarantees monotonicity. feedthru, is the measure of the und esirable switching noise coupled to the output. output voltage full scale settling time, is the time required from the 50% point on the clock input for a full scale step to settle within an 1 / 2 lsb error band. output voltage small scale settling time, is the time required from the 50% point on the clock input for a 100mv step to settle within an 1 / 2 lsb error band. this is used by applications reconstructing highly correlated signals such as sine waves with more th an 5 points per cycle. glitch area, ge, is the switching transient appearing on the output during a code transition. it is measured as the area under the curve and expressed as a picovolt-time specification (typically pv-s). differential gain, ? a v , is the gain error from an ideal sine wave with a normalized amplitude. differential phase, ? , is the phase error from an ideal sine wave. signal to noi se ratio, snr, is the ratio of a fundamental to the noise floor of the analog output. the first 5 harmonics are ignored, and an output filter of 1 / 2 the clock frequency is used to eliminate alias products. total harmonic distortion, thd, is the ratio of the dac output fundamental to the rms sum of the harmonics. the first 5 harmonics are included, and an output filter of 1 / 2 the clock frequency is used to eliminate alias products. spurious free dynamic range, sfdr , is the amplitude difference from a fundamental to the largest harmonically or non-harmonically related spur. a sine wave is loaded into the d/a and the output filtered at 1 / 2 the clock frequency to eliminate noise from clocking alias terms. intermodulation distortion, imd, is the measure of the sum and difference products produced when a two tone input is driven into the d/a. the distortion products created will arise at sum and difference frequencies of the two tones. imd can be calculated using the following equation: table 3. phase modulation input coding p1 p0 phase shift (degrees) 00 0 01 90 1 0 270 1 1 180 imd 20log (rms of sum and difference distortion products) rms amplitude of the fundamental () ------------------------------------------------------------------------------------------------------------------------------- ----------------------- - . = HI5731
13 encoder controller baseband bit stream k9 c11 b11 33msps clk clk mod2 mod1 hsp45106 sin15 r4 50 1 2 3 4 5 6 7 8 9 10 15 28 17 18 u2 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 dv cc v cc 16 u1 clk dgnd HI5731 dv ee dgnd -5.2v_d av ee av ss i out i out cntrl out cntrl in r set aret ref out 21 20 24 25 26 23 19 27 22 r1 64 r2 64 r3 976 c2 0.1 f c1 0.01 f -5.2v_a -5.2v_a filter to rf up-convert stage l2 10 h l1 10 h -5.2v_a -5.2v_d c10 mod0 a11 f10 f9 f11 h11 g11 g9 j11 g10 d10 j10 k11 b8 b6 b7 a7 c7 c6 a6 a5 c5 a4 b4 a3 a2 b3 a1 b10 b9 a10 e11 e9 h10 k2 j2 a8 v cc v cc v cc pmsel enporeg enofreg encfreg enphac entireg inhofr initpac inittac test parser binfmt c15_msb c4 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 a2 a1 a0 cs wr paci oes oec dacstrb sin14 sin13 sin12 sin11 sin10 sin9 sin8 sin7 sin6 sin5 sin4 sin3 sin2 sin1 sin0 l1 k3 l2 l3 l4 j5 k5 l5 k6 j6 j7 l7 l6 l8 k8 l9 l10 cos15 cos14 cos13 cos12 cos11 cos10 cos9 cos8 cos7 cos6 cos5 cos4 cos3 cos2 cos1 cos0 tico c2 b1 c1 d1 e3 e2 e1 f2 f3 g3 g1 g2 h1 h2 j1 k1 b2 11 12 d1 d0 (lsb) -5.2v_a figure 28. modulator using the HI5731 and the hsp45106 16-bit nco HI5731
14 encoder controller baseband bit stream control bus 16 19 20 18 17 12 9 14 13 10 11 i q 40msps clk clk p1 p0 load# txfr# enphac# sel_l/m# sclk sd sften# msb/lsb# hsp45102 out11 out10 out9 out8 out7 out6 out5 out4 out3 out2 out1 out0 6 5 4 3 2 1 28 27 26 25 24 23 r4 50 u1 l2 10 h l1 10 h -5.2v_a -5.2v_d 1 2 3 4 5 6 7 8 9 10 15 28 17 18 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 dv cc v cc 16 u2 clk dgnd HI5731 dv ee dgnd -5.2v_d av ee av ss i out i out cntrl out cntrl in rset aret ref out 21 20 24 25 26 23 19 27 22 r1 64 r2 64 r3 976 c2 0.1 f c1 0.01 f -5.2v_a -5.2v_a filter to rf up-convert stage 11 12 d1 d0 (lsb) -5.2v_a figure 29. psk modulator using the HI5731 and the hsp45102 12-bit nco HI5731
15 die characteristics die dimensions 161.5 mils x 160.7 mils x 19 mils metallization type: alsicu thickness: m1 - 8k ? , m2 - 17k ? passivation type: sandwich passivation undoped silicon glass (usg) + nitride thickness: usg - 8k ? , nitride - 4.2k ? total 12.2k ? + 2k ? substrate potential (powered up) v eed metallization mask layout HI5731 d8 d9 d10 d11 dgnd agnd ref out ctrl out i out i out artn dv ee dgnd dv cc clk d0 d1 d2 d3 d4 d5 d6 d7 r set av ee ctrl in HI5731
16 HI5731 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00
17 all intersil products are manuf actured, assembled and tested utilizing iso90 00 quality systems. intersil corporation?s quality certifications can be viewed at website www.i ntersil.com/ design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by int ersil is believed to be accurate and reliable. how- ever, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other r ights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site www.intersil.com HI5731 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93

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